dblp.uni-trier.dewww.uni-trier.de

Victor Navarro-Botello

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2009
3EEHéctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, J. Sosa, José C. García: A geometric approach to register transfer level satisfiability. ISQED 2009: 272-275
2007
2EEVictor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi: High performance low power CMOS dynamic logic for arithmetic circuits. Microelectronics Journal 38(4-5): 482-488 (2007)
2006
1EEVictor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi: Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications. J. Low Power Electronics 2(2): 300-307 (2006)

Coauthor Index

1José C. García [3]
2Juan A. Montiel-Nelson [1] [2] [3]
3Héctor Navarro [3]
4Saeid Nooshabadi [1] [2] [3]
5J. Sosa [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)