Bogdan Matasaru

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2000

1 EE Bogdan Matasaru, Tudor Jebelean: FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers. FPL 2000: 810-813

2000
1	EE	Bogdan Matasaru, Tudor Jebelean: FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers. FPL 2000: 810-813

Coauthor Index

1 Tudor Jebelean [1]