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Chi-Sheng Lin

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2006
5EERuei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu: A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. APCCAS 2006: 426-429
2004
4EEHui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu: A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. ISLPED 2004: 252-256
2003
3EEChi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu: Low-power and low-voltage fully parallel content-addressable memory. ISCAS (5) 2003: 373-376
2002
2EEShin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu: A scalable sorting architecture based on maskable WTA/MAX circuit. ISCAS (4) 2002: 209-212
1EEChi-Sheng Lin, Bin-Da Liu: Design of a pipelined and expandable sorting architecture with simple control scheme. ISCAS (4) 2002: 217-220

Coauthor Index

1Kuan-Hua Chen [3]
2Bin-Da Liu [1] [2] [3] [4] [5]
3Hsin-Hung Ou [4]
4Shin-Hong Ou [2]
5Hsin-Wen Ting [5]
6Ruei-Jhe Tsai [5]
7Hui-Chin Tseng [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)