| 2006 |
|---|
| 5 | EE | Ruei-Jhe Tsai,
Hsin-Wen Ting,
Chi-Sheng Lin,
Bin-Da Liu:
A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design.
APCCAS 2006: 426-429 |
| 2004 |
|---|
| 4 | EE | Hui-Chin Tseng,
Hsin-Hung Ou,
Chi-Sheng Lin,
Bin-Da Liu:
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach.
ISLPED 2004: 252-256 |
| 2003 |
|---|
| 3 | EE | Chi-Sheng Lin,
Kuan-Hua Chen,
Bin-Da Liu:
Low-power and low-voltage fully parallel content-addressable memory.
ISCAS (5) 2003: 373-376 |
| 2002 |
|---|
| 2 | EE | Shin-Hong Ou,
Chi-Sheng Lin,
Bin-Da Liu:
A scalable sorting architecture based on maskable WTA/MAX circuit.
ISCAS (4) 2002: 209-212 |
| 1 | EE | Chi-Sheng Lin,
Bin-Da Liu:
Design of a pipelined and expandable sorting architecture with simple control scheme.
ISCAS (4) 2002: 217-220 |
