| |
| 2007 | ||
|---|---|---|
| 4 | EE | Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi: A fast clock scheduling for peak power reduction in LSI. ACM Great Lakes Symposium on VLSI 2007: 582-587 |
| 3 | EE | Yukihide Kohira, Atsushi Takahashi: A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. ISCAS 2007: 1795-1798 |
| 2 | EE | Yukihide Kohira, Atsushi Takahashi: Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. IEICE Transactions 90-A(4): 800-807 (2007) |
| 2005 | ||
| 1 | EE | Yukihide Kohira, Atsushi Takahashi: Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion. IEICE Transactions 88-A(4): 892-898 (2005) |
| 1 | Atsushi Takahashi | [1] [2] [3] [4] |
| 2 | Yosuke Takahashi | [4] |