| 2009 |
|---|
| 17 | EE | Shuichi Ichikawa,
Sho Takahashi,
Yuu Kawai:
Optimizing process allocation of parallel programs for heterogeneous clusters.
Concurrency and Computation: Practice and Experience 21(4): 475-507 (2009) |
| 2008 |
|---|
| 16 | EE | Shuichi Ichikawa,
Takashi Sawada,
Hisashi Hata:
Diversification of Processors Based on Redundancy in Instruction Set.
IEICE Transactions 91-A(1): 211-220 (2008) |
| 2006 |
|---|
| 15 | EE | Kazuhiro Hattanda,
Shuichi Ichikawa:
Redundancy in Instruction Sequences of Computer Programs.
IEICE Transactions 89-A(1): 219-221 (2006) |
| 14 | EE | Ryoichiro Atono,
Shuichi Ichikawa:
Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm.
IEICE Transactions 89-D(7): 2301-2305 (2006) |
| 2005 |
|---|
| 13 | EE | Shiro Konuma,
Shuichi Ichikawa:
Design and Evaluation of Hardware Pseudo-Random Number Generator MT19937.
IEICE Transactions 88-D(12): 2876-2879 (2005) |
| 12 | EE | Yoshinori Kishimoto,
Shuichi Ichikawa:
Optimizing the configuration of a heterogeneous cluster with multiprocessing and execution-time estimation.
Parallel Computing 31(7): 691-710 (2005) |
| 2004 |
|---|
| 11 | EE | Yoshinori Kishimoto,
Shuichi Ichikawa:
An Execution-Time Estimation Model for Heterogeneous Clusters.
IPDPS 2004 |
| 10 | EE | Kazuhiro Hattanda,
Shuichi Ichikawa:
The Evaluation of Davidson's Digital Signature Scheme.
IEICE Transactions 87-A(1): 224-225 (2004) |
| 2003 |
|---|
| 9 | EE | Shoji Yamamoto,
Shuichi Ichikawa,
Hiroshi Yamamoto:
Data Dependent Circuit Design: A Case Study.
FPL 2003: 1024-1027 |
| 2002 |
|---|
| 8 | EE | Shuichi Ichikawa,
Shoji Yamamoto:
Data Dependent Circuit for Subgraph Isomorphism Problem.
FPL 2002: 1068-1071 |
| 7 | EE | Shuichi Ichikawa,
H. Chiyama,
K. Akabane:
Redundancy in 3D Polygon Models and Its Application to Digital Signature.
WSCG 2002: 225-232 |
| 2000 |
|---|
| 6 | EE | Shuichi Ichikawa,
Lerdtanaseangtham Udorn,
Kouji Konishi:
Hardware Accelerator for Subgraph Isomorphism Problems.
FCCM 2000: 283-284 |
| 5 | EE | Shuichi Ichikawa,
Hidemitsu Saito,
Lerdtanaseangtham Udorn,
Kouji Konishi:
Evaluation of Accelerator Designs for Subgraph Isomorphism Problem.
FPL 2000: 729-738 |
| 1991 |
|---|
| 4 | | N. Yoshida,
Eiichi Goto,
Shuichi Ichikawa:
Pseudorandom Rounding for Truncated Multipliers.
IEEE Trans. Computers 40(9): 1065-1067 (1991) |
| 1990 |
|---|
| 3 | EE | Mitsuhisa Sato,
Shuichi Ichikawa,
Eiichi Goto:
Multiple instruction streams in a highly pipelined processor.
SPDP 1990: 182-189 |
| 1989 |
|---|
| 2 | EE | Mitsuhisa Sato,
Shuichi Ichikawa,
Eiichi Goto:
Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking.
ISCA 1989: 290-297 |
| 1 | | Kentaro Shimizu,
Eiichi Goto,
Shuichi Ichikawa:
CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines.
IEEE Trans. Computers 38(6): 825-832 (1989) |
