| |
| 2005 | ||
|---|---|---|
| 12 | EE | Ahmad A. Hiasat: VLSI implementation of new arithmetic residue to binary decoders. IEEE Trans. VLSI Syst. 13(1): 153-158 (2005) |
| 2004 | ||
| 11 | EE | Ahmad A. Hiasat: A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2n - (2p [plusmn] 1)). Comput. J. 47(1): 93-102 (2004) |
| 10 | Ahmad A. Hiasat: A Suggestion for a New RNS-Based Multiplier for a Family of Moduli. I. J. Comput. Appl. 11(2): 92-97 (2004) | |
| 2003 | ||
| 9 | EE | Ahmad A. Hiasat: An arithmetic residue to binary conversion technique. Integration 36(1-2): 13-25 (2003) |
| 8 | EE | Ahmad A. Hiasat, Omar Hasan: Bit-serial architecture for rank order and stack filters. Integration 36(1-2): 3-12 (2003) |
| 7 | EE | Ahmad A. Hiasat, Andraos Sweidan: Residue number system to binary converter for the moduli set (2n-1, 2n-1, 2n+1). Journal of Systems Architecture 49(1-2): 53-58 (2003) |
| 2002 | ||
| 6 | EE | Ahmad A. Hiasat: High-Speed and Reduced-Area Modular Adder Structures for RNS. IEEE Trans. Computers 51(1): 84-89 (2002) |
| 2001 | ||
| 5 | EE | Andraos Sweidan, Ahmad A. Hiasat: On the Theory of Error Control Based on Moduli with Common Factors. Reliable Computing 7(3): 209-218 (2001) |
| 2000 | ||
| 4 | EE | Ahmad A. Hiasat: New Efficient Structure for a Modular Multiplier for RNS. IEEE Trans. Computers 49(2): 170-174 (2000) |
| 1999 | ||
| 3 | Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy: Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm. Comput. J. 42(3): 232-240 (1999) | |
| 1997 | ||
| 2 | EE | Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy: Design and Implementation of An RNS Division Algorithmm. IEEE Symposium on Computer Arithmetic 1997: 240-249 |
| 1995 | ||
| 1 | Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy: High-Speed Division Algorithm for Residue Number System. ISCAS 1995: 1996-1999 | |
| 1 | Hoda S. Abdel-Aty-Zohdy | [1] [2] [3] |
| 2 | Omar Hasan | [8] |
| 3 | Andraos Sweidan | [5] [7] |