Fran Hancheck
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1996
1
EE
Fran Hancheck,
Shantanu Dutt
: Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs.
ICCD 1996
: 326-331
Coauthor
Index
1
Shantanu Dutt
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
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