| 2005 |
|---|
| 4 | EE | Manish Garg,
A. Kumar,
J. van Wingerden,
Laurent Le Cam:
Litho-driven layouts for reducing performance variability.
ISCAS (4) 2005: 3551-3554 |
| 3 | EE | Manish Garg,
Laurent Le Cam,
Matthieu Gonzalez:
Lithography Driven Layout Design.
VLSI Design 2005: 439-444 |
| 2 | EE | Andrei Terechko,
Manish Garg,
Henk Corporaal:
Evaluation of Speed and Area of Clustered VLIW Processors.
VLSI Design 2005: 557-563 |
| 2003 |
|---|
| 1 | EE | Andrei Terechko,
Erwan Le Thenaff,
Manish Garg,
Jos T. J. van Eijndhoven,
Henk Corporaal:
Inter-Cluster Communication Models for Clustered VLIW Processors.
HPCA 2003: 354-364 |
