T. Egan
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2005
1
EE
T. Egan,
S. Mourad
: Design-for-testability for embedded delay-locked loops.
IEEE Trans. VLSI Syst. 13
(8): 984-988 (2005)
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1
S. Mourad
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Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
