Ahmet Dervisoglu
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1999
1
EE
Siddika Berna Örs
, Ahmet Dervisoglu: Modeling Bit Multiplication Blocks for DSP Applications Using VHDL.
EUROMICRO 1999
: 1402-1405
Coauthor
Index
1
Siddika Berna Örs
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1
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Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
