K. De

List of publications from the DBLP Bibliography Server - FAQ

1997

3 EE K. De: Test methodology for embedded cores which protects intellectual property. VTS 1997: 2-9

1994

2 EE K. De, C. Natarajan, D. Nair, P. Banerjee: RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans. VLSI Syst. 2(2): 186-195 (1994)

1993

1 EE K. De, P. Banerjee: PREST: a system for logic partitioning and resynthesis for testability. IEEE Trans. VLSI Syst. 1(4): 514-525 (1993)

1997
3	EE	K. De: Test methodology for embedded cores which protects intellectual property. VTS 1997: 2-9
1994
2	EE	K. De, C. Natarajan, D. Nair, P. Banerjee: RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans. VLSI Syst. 2(2): 186-195 (1994)
1993
1	EE	K. De, P. Banerjee: PREST: a system for logic partitioning and resynthesis for testability. IEEE Trans. VLSI Syst. 1(4): 514-525 (1993)

Coauthor Index