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K. De

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1997
3EEK. De: Test methodology for embedded cores which protects intellectual property. VTS 1997: 2-9
1994
2EEK. De, C. Natarajan, D. Nair, P. Banerjee: RSYN: a system for automated synthesis of reliable multilevel circuits. IEEE Trans. VLSI Syst. 2(2): 186-195 (1994)
1993
1EEK. De, P. Banerjee: PREST: a system for logic partitioning and resynthesis for testability. IEEE Trans. VLSI Syst. 1(4): 514-525 (1993)

Coauthor Index

1P. Banerjee [1] [2]
2D. Nair [2]
3C. Natarajan [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)