| 2008 |
|---|
| 3 | EE | Yogesh Singh Chauhan,
D. Tsamados,
Nicolas Abelé,
C. Eggimann,
Michel J. Declercq,
Adrian M. Ionescu:
Compact Modeling of Suspended Gate FET.
VLSI Design 2008: 119-124 |
| 2007 |
|---|
| 2 | EE | Yogesh Singh Chauhan,
Francois Krummenacher,
Renaud Gillon,
Benoit Bakeroot,
Michel J. Declercq,
Adrian M. Ionescu:
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.
VLSI Design 2007: 177-182 |
| 2006 |
|---|
| 1 | EE | Yogesh Singh Chauhan,
C. Anghel,
Francois Krummenacher,
Renaud Gillon,
A. Baguenier:
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor.
ISQED 2006: 109-114 |
