2007 | ||
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2 | EE | Subhomoy Chattopadhyay: Low power design techniques for nanometer design processes: 65 nm and smaller. SBCCI 2007: 5 |
1 | EE | Subhomoy Chattopadhyay, Rakesh Patel: Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. VLSI Design 2007: 5 |
1 | Rakesh Patel | [1] |