| |
| 2005 | ||
|---|---|---|
| 3 | EE | Rami Beidas, Jianwen Zhu: Scalable interprocedural register allocation for high level synthesis. ASP-DAC 2005: 511-516 |
| 2004 | ||
| 2 | Rami Beidas, Jianwen Zhu: A queuing-theoretic performance model for context-flow system-on-chip platforms. ESTImedia 2004: 21-26 | |
| 2003 | ||
| 1 | EE | Rami Beidas, Jianwen Zhu: Performance Efficiency of Context-Flow System-on-Chip Platform. ICCAD 2003: 356-362 |
| 1 | Jianwen Zhu | [1] [2] [3] |