| 2008 |
|---|
| 4 | EE | Georg Hager,
Thomas Zeiser,
Gerhard Wellein:
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers.
IPDPS 2008: 1-7 |
| 2007 |
|---|
| 3 | EE | Georg Hager,
Thomas Zeiser,
Gerhard Wellein:
Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers
CoRR abs/0712.2302: (2007) |
| 2 | EE | Georg Hager,
Holger Stengel,
Thomas Zeiser,
Gerhard Wellein:
RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks
CoRR abs/0712.3389: (2007) |
| 2004 |
|---|
| 1 | EE | Thomas Pohl,
Frank Deserno,
Nils Thürey,
Ulrich Rüde,
Peter Lammers,
Gerhard Wellein,
Thomas Zeiser:
Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures.
SC 2004: 21 |
