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Thomas Zeiser

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2008
4EEGeorg Hager, Thomas Zeiser, Gerhard Wellein: Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers. IPDPS 2008: 1-7
2007
3EEGeorg Hager, Thomas Zeiser, Gerhard Wellein: Data access optimizations for highly threaded multi-core CPUs with multiple memory controllers CoRR abs/0712.2302: (2007)
2EEGeorg Hager, Holger Stengel, Thomas Zeiser, Gerhard Wellein: RZBENCH: Performance evaluation of current HPC architectures using low-level and application benchmarks CoRR abs/0712.3389: (2007)
2004
1EEThomas Pohl, Frank Deserno, Nils Thürey, Ulrich Rüde, Peter Lammers, Gerhard Wellein, Thomas Zeiser: Performance Evaluation of Parallel Large-Scale Lattice Boltzmann Applications on Three Supercomputing Architectures. SC 2004: 21

Coauthor Index

1Frank Deserno [1]
2Georg Hager [2] [3] [4]
3Peter Lammers [1]
4Thomas Pohl [1]
5Ulrich Rüde [1]
6Holger Stengel [2]
7Nils Thürey [1]
8Gerhard Wellein [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)