| |
| 2008 | ||
|---|---|---|
| 3 | EE | Chao Yan, Mark R. Greenstreet: Faster projection based methods for circuit level verification. ASP-DAC 2008: 410-415 |
| 2007 | ||
| 2 | EE | Chao Yan, Mark R. Greenstreet: Circuit Level Verification of a High-Speed Toggle. FMCAD 2007: 199-206 |
| 2004 | ||
| 1 | EE | Chao Yan, Guo-Liang Chen, Yi-Fei Shen: Outleir Analysis for Gene Expression Data. J. Comput. Sci. Technol. 19(1): 13-21 (2004) |
| 1 | Guo-Liang Chen | [1] |
| 2 | Mark R. Greenstreet | [2] [3] |
| 3 | Yi-Fei Shen | [1] |