| |
| 2007 | ||
|---|---|---|
| 2 | EE | Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang: A 64-bit stream processor architecture for scientific applications. ISCA 2007: 210-219 |
| 2006 | ||
| 1 | EE | Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing: An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. Asia-Pacific Computer Systems Architecture Conference 2006: 588-594 |
| 1 | Yu Deng | [2] |
| 2 | Jiang Jiang | [2] |
| 3 | Xiaobo Yan | [2] |
| 4 | Xuejun Yang | [2] |
| 5 | Chengyi Zhang | [1] |
| 6 | Minxuan Zhang | [1] |
| 7 | Ying Zhang | [2] |
| 8 | Hongwei Zhou | [1] |