| 2003 |
|---|
| 6 | EE | Poul Frederick Williams,
Henrik Reif Andersen,
Henrik Hulgaard:
Satisfiability checking using Boolean Expression Diagrams.
STTT 5(1): 4-14 (2003) |
| 2001 |
|---|
| 5 | EE | Poul Frederick Williams,
Henrik Reif Andersen,
Henrik Hulgaard:
Satisfiability Checking Using Boolean Expression Diagrams.
TACAS 2001: 39-51 |
| 4 | EE | Poul Frederick Williams:
Formal Verification based on Boolean Expression Diagrams.
Electr. Notes Theor. Comput. Sci. 56: (2001) |
| 2000 |
|---|
| 3 | | Poul Frederick Williams,
Armin Biere,
Edmund M. Clarke,
Anubhav Gupta:
Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking.
CAV 2000: 124-138 |
| 2 | EE | Poul Frederick Williams,
Macha Nikolskaïa,
Antoine Rauzy:
Bypassing BDD construction for reliability analysis.
Inf. Process. Lett. 75(1-2): 85-89 (2000) |
| 1999 |
|---|
| 1 | EE | Henrik Hulgaard,
Poul Frederick Williams,
Henrik Reif Andersen:
Equivalence checking of combinational circuits using Boolean expression diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 903-917 (1999) |
