Yuanzhong Wan

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2005

2 EE Yuanzhong Wan, Maitham Shams: Delay modeling of CMOS/CPL logic circuits. ISCAS (6) 2005: 5613-5616

1 EE Yuanzhong Wan, Maitham Shams: Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. VLSI Design 2005: 261-266

2005
2	EE	Yuanzhong Wan, Maitham Shams: Delay modeling of CMOS/CPL logic circuits. ISCAS (6) 2005: 5613-5616
1	EE	Yuanzhong Wan, Maitham Shams: Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder. VLSI Design 2005: 261-266

Coauthor Index

1 Maitham Shams [1] [2]