| |
| 2008 | ||
|---|---|---|
| 3 | EE | Sergey Tverdyshev, Eyad Alkassar: Efficient Bit-Level Model Reductions for Automated Hardware Verification. TIME 2008: 164-172 |
| 2007 | ||
| 2 | EE | Eyad Alkassar, Mark A. Hillebrand, Steffen Knapp, Rostislav Rusev, Sergey Tverdyshev: Formal Device and Programming Model for a Serial Interface. VERIFY 2007 |
| 2005 | ||
| 1 | EE | Sergey Tverdyshev: Combination of Isabelle/HOL with Automatic Tools. FroCos 2005: 302-309 |
| 1 | Eyad Alkassar | [2] [3] |
| 2 | Mark A. Hillebrand | [2] |
| 3 | Steffen Knapp | [2] |
| 4 | Rostislav Rusev | [2] |