| |
| 2008 | ||
|---|---|---|
| 2 | Thanasin Bunnam, Arthit Thongtak: An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits. CDES 2008: 224-228 | |
| 1998 | ||
| 1 | EE | Arthit Thongtak, Takashi Nanya: Stuck-at-fault testing for quasi-delay-insensitive logic circuits. Systems and Computers in Japan 29(2): 19-27 (1998) |
| 1 | Thanasin Bunnam | [2] |
| 2 | Takashi Nanya | [1] |