| 2008 |
|---|
| 19 | EE | Masaru Takesue:
A Protection Scheme against the Attacks Deployed by Hiding the Violation of the Same Origin Policy.
SECURWARE 2008: 133-138 |
| 2007 |
|---|
| 18 | EE | Masaru Takesue:
The SKB: A Semi-Completely-Connected Bus for On-Chip Systems.
NPC 2007: 404-414 |
| 17 | EE | Masaru Takesue:
A Scheme for Protecting the Information Leakage Via Portable Devices.
SECURWARE 2007: 54-59 |
| 2006 |
|---|
| 16 | | Masaru Takesue:
A Bus-Based Recursive Mesh for High-Performance On-Chip Systems.
ISCA PDCS 2006: 13-18 |
| 15 | EE | Masaru Takesue:
The psi-cube: a bus-based cube-type clustering network for high-performance on-chip systems.
Parallel Computing 32(11-12): 852-869 (2006) |
| 2005 |
|---|
| 14 | EE | Masaru Takesue:
The Psi-Cube: A Bus-Based Cube-Type Network for High-Performance On-Chip Systems.
ICPP Workshops 2005: 539-546 |
| 2004 |
|---|
| 13 | EE | Masaru Takesue:
DC-mesh: A Contracted High-Dimensional Mesh for Dynamic Clustering.
NPC 2004: 382-389 |
| 2003 |
|---|
| 12 | EE | Masaru Takesue:
A Model of Pipelined Mutual Exclusion on Cache-Coherent Multiprocessors.
Euro-Par 2003: 917-922 |
| 11 | EE | Masaru Takesue:
Software Queue-Based Algorithms for Pipelined Synchronization on Multiprocessors.
ICPP Workshops 2003: 115-122 |
| 10 | | Masaru Takesue:
Pipelined Conditional Synchronization on Large-Scale Cache-Coherent Multiprocessors.
ISCA PDCS 2003: 132-138 |
| 2002 |
|---|
| 9 | | Masaru Takesue:
Pipelined Mutual Exclusion on Large-scale Cachecoherent Multiprocessors.
IASTED PDCS 2002: 736-745 |
| 1999 |
|---|
| 8 | EE | Masaru Takesue:
Psi-Cubes: Recursive Bused Fat-Hypercubes for Multilevel Snoopy Caches.
ISPAN 1999: 62-67 |
| 1998 |
|---|
| 7 | EE | Masaru Takesue:
Schemes for Reducing Communication Latency in Regular Computations on DSM Multiprocessors.
ICPP 1998: 164-171 |
| 1997 |
|---|
| 6 | EE | Masaru Takesue:
A tampering protocol for reducing the coherence transactions in regular computation.
ISPAN 1997: 465-471 |
| 1993 |
|---|
| 5 | EE | Masaru Takesue:
A Family of Parallel Prefix Algorithms Embedded in Networks.
IEEE Trans. Parallel Distrib. Syst. 4(10): 1179-1184 (1993) |
| 1992 |
|---|
| 4 | | Masaru Takesue:
Cache Memories for Data Flow Machines.
IEEE Trans. Computers 41(6): 677-687 (1992) |
| 1989 |
|---|
| 3 | | Masaru Takesue:
Dataflow Computer Extension Towards Real-Time Processing.
Real-Time Systems 1(4): 333-350 (1989) |
| 1987 |
|---|
| 2 | | Masaru Takesue:
A Unified Resource Management and Execution Control Mechanism for Data Flow Machines.
ISCA 1987: 90-97 |
| 1986 |
|---|
| 1 | | Makoto Amamiya,
Masaru Takesue,
Ryuzo Hasegawa,
Hirohide Mikami:
Implementation and Evaluation of a List-Processing-Oriented Data Flow Machine.
ISCA 1986: 10-19 |
