| |
| 2007 | ||
|---|---|---|
| 8 | EE | Paul B. Jackson, Daniel Sheridan: A Compact Linear Translation for Bounded Model Checking. Electr. Notes Theor. Comput. Sci. 174(3): 17-30 (2007) |
| 2005 | ||
| 7 | EE | Daniel Sheridan: Bounded Model Checking with SNF, Alternating Automata, and Bu"chi Automata. Electr. Notes Theor. Comput. Sci. 119(2): 83-101 (2005) |
| 2004 | ||
| 6 | EE | Alessandro Cimatti, Marco Roveri, Daniel Sheridan: Bounded Verification of Past LTL. FMCAD 2004: 245-259 |
| 5 | EE | Daniel Sheridan: The Optimality of a Fast CNF Conversion and its Use with SAT. SAT 2004 |
| 4 | EE | Paul Jackson, Daniel Sheridan: Clause Form Conversions for Boolean Circuits. SAT (Selected Papers 2004: 183-198 |
| 2003 | ||
| 3 | EE | Daniel Sheridan: Dynamic Step Size Adjustment in Iterative Deepening Search. CP 2003: 996 |
| 2002 | ||
| 2 | EE | Alan M. Frisch, Daniel Sheridan, Toby Walsh: A Fixpoint Based Encoding for Bounded Model Checking. FMCAD 2002: 238-255 |
| 2001 | ||
| 1 | EE | Daniel Sheridan: Comparing SAT Encodings for Model Checking. CP 2001: 784 |
| 1 | Alessandro Cimatti | [6] |
| 2 | Alan M. Frisch | [2] |
| 3 | Paul Jackson | [4] |
| 4 | Paul B. Jackson | [8] |
| 5 | Marco Roveri | [6] |
| 6 | Toby Walsh | [2] |