R. Seshasayanan

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2005

1 Arun Vijayaraghavan, M. Kannan, R. Seshasayanan: Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency. CDES 2005: 143-152

2005
1		Arun Vijayaraghavan, M. Kannan, R. Seshasayanan: Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency. CDES 2005: 143-152

Coauthor Index

1 M. Kannan [1]

2 Arun Vijayaraghavan [1]