Chaitanya Sathe
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2007
1
EE
Chaitanya Sathe,
Santanu Mahapatra
: Modeling and Analysis of Noise Margin in SET Logic.
VLSI Design 2007
: 207-214
Coauthor
Index
1
Santanu Mahapatra
[
1
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Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
