| |
| 2002 | ||
|---|---|---|
| 2 | EE | A. Salem: Semi-formal verification of VHDL-AMS descriptions. ISCAS (5) 2002: 333-336 |
| 2001 | ||
| 1 | EE | Sherief Reda, A. Salem: Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. DATE 2001: 122-126 |
| 1 | Sherief Reda | [1] |