Leonard M. Napolitano Jr.

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1993

3 G. Robert Redinbo, Leonard M. Napolitano Jr., David D. Andaleon: Multibit Correcting Data Interface for Fault-Tolerant Systems. IEEE Trans. Computers 42(4): 433-446 (1993)

1990

2 Leonard M. Napolitano Jr.: The Design of a High Performance Packet-Switched Network. J. Parallel Distrib. Comput. 10(2): 103-114 (1990)

1986

1 Leonard M. Napolitano Jr.: A Computer Architecture for Dynamic Finite Element Analysis. ISCA 1986: 316-323

1993
3		G. Robert Redinbo, Leonard M. Napolitano Jr., David D. Andaleon: Multibit Correcting Data Interface for Fault-Tolerant Systems. IEEE Trans. Computers 42(4): 433-446 (1993)
1990
2		Leonard M. Napolitano Jr.: The Design of a High Performance Packet-Switched Network. J. Parallel Distrib. Comput. 10(2): 103-114 (1990)
1986
1		Leonard M. Napolitano Jr.: A Computer Architecture for Dynamic Finite Element Analysis. ISCA 1986: 316-323

Coauthor Index

1 David D. Andaleon [3]

2 G. Robert Redinbo [3]