| |
| 2007 | ||
|---|---|---|
| 4 | EE | Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima: An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators. Annual Simulation Symposium 2007: 247-255 |
| 2006 | ||
| 3 | EE | Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima: Design and Implementation of aWorkload Specific Simulator. Annual Simulation Symposium 2006: 230-243 |
| 2 | EE | Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada: An accurate and efficient simulation-based analysis for worst case interruption delay. CASES 2006: 2-12 |
| 2004 | ||
| 1 | EE | Takashi Nakada, Hiroshi Nakashima: Design and Implementation of a High Speed Microprocessor Simulator BurstScalar. MASCOTS 2004: 364-372 |
| 1 | Masahiro Konishi | [2] |
| 2 | Hiroshi Nakashima | [1] [2] [3] [4] |
| 3 | Toru Takasaki | [4] |
| 4 | Tomoaki Tsumura | [3] |
| 5 | Masahiro Yano | [4] |