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1995 | ||
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2 | EE | J. T. Mowchenko, Y. Yang: Optimizing wiring space in slicing floorplans. Great Lakes Symposium on VLSI 1995: 54- |
1989 | ||
1 | EE | J. T. Mowchenko: A lower bound on channel density after global routing. IEEE Trans. on CAD of Integrated Circuits and Systems 8(5): 574-577 (1989) |
1 | Y. Yang | [2] |