Seiji Miura

List of publications from the DBLP Bibliography Server - FAQ

2005

2 EE Seiji Miura, Satoru Akiyama: A memory controller that reduces latency of cached SDRAM. ISCAS (5) 2005: 5250-5253

2001

1 EE Seiji Miura, Kazushige Ayukawa, Takao Watanabe: A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. ISLPED 2001: 358-363

2005
2	EE	Seiji Miura, Satoru Akiyama: A memory controller that reduces latency of cached SDRAM. ISCAS (5) 2005: 5250-5253
2001
1	EE	Seiji Miura, Kazushige Ayukawa, Takao Watanabe: A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. ISLPED 2001: 358-363

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