| |
| 2007 | ||
|---|---|---|
| 3 | EE | Hua Li, Jianzhou Li: A New Compact Architecture for AES with Optimized ShiftRows Operation. ISCAS 2007: 1851-1854 |
| 2006 | ||
| 2 | Hua Li, Chang Nian Zhang, Jianzhou Li: A CAM Based Associative Processor Array for Parallel Implementation of AES. I. J. Comput. Appl. 13(4): 176-181 (2006) | |
| 2005 | ||
| 1 | EE | Hua Li, Jianzhou Li: A High Performance Sub-Pipelined Architecture for AES. ICCD 2005: 491-496 |
| 1 | Hua Li | [1] [2] [3] |
| 2 | Chang Nian Zhang (Chang N. Zhang) | [2] |