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Y. Y. H. Lam

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1997
2 C. C. Jong, Y. Y. H. Lam, L. S. Ng: FPGA implementation of a digital IQ demodulator using VHDL. FPL 1997: 410-417
1994
1 C. C. Jong, Y. Y. H. Lam, S. S. Lim, T. S. Teng: Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. ISCAS 1994: 37-40

Coauthor Index

1C. C. Jong [1] [2]
2S. S. Lim [1]
3L. S. Ng [2]
4T. S. Teng [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)