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| 1997 | ||
|---|---|---|
| 2 | C. C. Jong, Y. Y. H. Lam, L. S. Ng: FPGA implementation of a digital IQ demodulator using VHDL. FPL 1997: 410-417 | |
| 1994 | ||
| 1 | C. C. Jong, Y. Y. H. Lam, S. S. Lim, T. S. Teng: Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. ISCAS 1994: 37-40 | |
| 1 | C. C. Jong | [1] [2] |
| 2 | S. S. Lim | [1] |
| 3 | L. S. Ng | [2] |
| 4 | T. S. Teng | [1] |