| |
| 2008 | ||
|---|---|---|
| 2 | EE | Arun Janarthanan, Karen A. Tomko: MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks. VLSI Design 2008: 397-402 |
| 2007 | ||
| 1 | EE | Arun Janarthanan, Vijay Swaminathan, Karen A. Tomko: MoCReS: an Area-Efficient Multi-Clock On-Chip Network for Reconfigurable Systems. ISVLSI 2007: 455-456 |
| 1 | Vijay Swaminathan | [1] |
| 2 | Karen A. Tomko | [1] [2] |