| |
| 1991 | ||
|---|---|---|
| 1 | EE | Wen-Tsuen Chen, Jia-Shung Wang, Chia-Cheng Liu, Shi-Jinn Horng, Chang-Biau Yang, Ruey-Zone Huang, Bern-Cherng Liaw: Design of An Integrated Parallel Processing System with Systolic VLSI Chips. J. Inf. Sci. Eng. 7(2): 217-235 (1991) |
| 1 | Wen-Tsuen Chen | [1] |
| 2 | Shi-Jinn Horng | [1] |
| 3 | Bern-Cherng Liaw | [1] |
| 4 | Chia-Cheng Liu | [1] |
| 5 | Jia-Shung Wang | [1] |
| 6 | Chang-Biau Yang | [1] |