| |
| 1995 | ||
|---|---|---|
| 1 | EE | Giuseppe Caire, Javier Ventura-Traveset, M. Hollreiser, Ezio Biglieri: Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. VLSI Signal Processing 10(2): 153-168 (1995) |
| 1 | Ezio Biglieri | [1] |
| 2 | Giuseppe Caire | [1] |
| 3 | Javier Ventura-Traveset | [1] |