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2006 | ||
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1 | EE | Mitsutoshi Yahara, Kuniaki Fujimoto, Hirofumi Sasaki, Takashi Shibuya, Yoshinori Higashi: All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter. IEICE Transactions 89-A(6): 1527-1532 (2006) |
1 | Kuniaki Fujimoto | [1] |
2 | Hirofumi Sasaki | [1] |
3 | Takashi Shibuya | [1] |
4 | Mitsutoshi Yahara | [1] |