Sandi Habinc
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1996
1
EE
Sandi Habinc,
Peter Sinander
: Using VHDL for Board Level Simulation.
IEEE Design & Test of Computers 13
(3): 66-78 (1996)
Coauthor
Index
1
Peter Sinander
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
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