An-Te Deng
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2003
1
EE
An-Te Deng,
Winser E. Alexander
: Dual clock rate block data parallel architecture.
ISCAS (4) 2003
: 532-535
Coauthor
Index
1
Winser E. Alexander
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
