Che-Fu Chen

1995
1		Chin-Liang Wang, Ching-Chia Chen, Che-Fu Chen: A Digital-Serial VLSI Architecture for Delayed LMS Adaptive FIR Filttering. ISCAS 1995: 545-548

Coauthor Index

1	Ching-Chia Chen	[1]
2	Chin-Liang Wang	[1]