Vinay B. Chandratre

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2008

1 EE S. Balaji, Vinay B. Chandratre, Menka Tewani: 0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2008: 613-619

2008
1	EE	S. Balaji, Vinay B. Chandratre, Menka Tewani: 0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2008: 613-619

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