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1989 | ||
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1 | EE | Graham A. Jullien, P. D. Bird, J. T. Carr, M. Taheri, William C. Miller: An efficient bit-level systolic cell design for finite ring digital signal processing applications. VLSI Signal Processing 1(3): 189-207 (1989) |
1 | P. D. Bird | [1] |
2 | Graham A. Jullien | [1] |
3 | William C. Miller | [1] |
4 | M. Taheri | [1] |