| |
| 2005 | ||
|---|---|---|
| 2 | EE | Daniel H. Y. Teng, Ronald J. Bolton: Estimation of Average Multiple-Valued Logic Circuit Size Using Monte Carlo Simulation Technique. ISMVL 2005: 276-281 |
| 2004 | ||
| 1 | EE | Daniel H. Y. Teng, Ronald J. Bolton: A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications. ISMVL 2004: 204-209 |
| 1 | Daniel H. Y. Teng | [1] [2] |