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S. Bierly

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1985
1EEM. Iachponi, D. Vail, S. Bierly, A. Ignatowski: A hierarchical gate array architecture and design methodology. DAC 1985: 439-442

Coauthor Index

1M. Iachponi [1]
2A. Ignatowski [1]
3D. Vail [1]

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