| 1998 |
|---|
| 8 | EE | Rajiv Gupta,
David A. Berson,
Jesse Zhixi Fang:
Path Profile Guided Partial Redundancy Elimination Using Speculation.
ICCL 1998: 230-239 |
| 7 | EE | David A. Berson,
Rajiv Gupta,
Mary Lou Soffa:
Integrated Instruction Scheduling and Register Allocation Techniques.
LCPC 1998: 247-262 |
| 1997 |
|---|
| 6 | EE | Rajiv Gupta,
David A. Berson,
Jesse Zhixi Fang:
Path Profile Guided Partial Dead Code Elimation Using Predication.
IEEE PACT 1997: 102- |
| 5 | EE | Rajiv Gupta,
David A. Berson,
Jesse Zhixi Fang:
Resource-Sensitive Profile-Directed Data Flow Analysis for Code Optimization.
MICRO 1997: 358-368 |
| 1996 |
|---|
| 4 | | David A. Berson,
Pohua P. Chang,
Rajiv Gupta,
Mary Lou Soffa:
Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism.
LCPC 1996: 207-221 |
| 1995 |
|---|
| 3 | | David A. Berson,
Rajiv Gupta,
Mary Lou Soffa:
GURRR: A Global Unified Resource Requirements Representation.
Intermediate Representations Workshop 1995: 23-34 |
| 1994 |
|---|
| 2 | | David A. Berson,
Rajiv Gupta,
Mary Lou Soffa:
Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers.
IFIP PACT 1994: 135-146 |
| 1993 |
|---|
| 1 | | David A. Berson,
Rajiv Gupta,
Mary Lou Soffa:
URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures.
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism 1993: 243-254 |
