| |
| 1976 | ||
|---|---|---|
| 6 | Sheldon B. Akers Jr.: A Logic System for Fault Test Generation. IEEE Trans. Computers 25(6): 620-630 (1976) | |
| 1972 | ||
| 5 | Sheldon B. Akers Jr.: Universal Test Sets for Logic Networks FOCS 1972: 177-184 | |
| 1971 | ||
| 4 | Sheldon B. Akers Jr.: A Rectangular Logic Array FOCS 1971: 79-90 | |
| 1964 | ||
| 3 | Sheldon B. Akers Jr.: A diagrammatic approach to multi-level logic synthesis FOCS 1964: 165-173 | |
| 1962 | ||
| 2 | Sheldon B. Akers Jr.: Synthesis of combinational logic using three-input majority gates FOCS 1962: 149-157 | |
| 1961 | ||
| 1 | Sheldon B. Akers Jr.: Threshold logic and two-person, zero-sum games FOCS 1961: 27-33 | |